URSI High-speed Inter-MCU Connectivity

URSI - High-speed Inter-MCU Connectivity

The Universal Responsive Serial Interface (URSI) is an innovative modulation scheme that delivers the highest effective transfer rate at lowest over-sampling clock for PLL-less CDR across asynchronous sub-systems, low cost implementation and low power operation.


  • High Speed Asynchronous Single Wire or LVDS pair Serial Communication
  • Lowest 3.5x Over-sampling PLL-less Decoder per bits to reach Gbps performance
  • Lower Cost and Power Gbps link compared to SERDES
  • Responsive Interface with 3 bits of latency
  • Wide tolerance of ±20% clock mismatch between the receiver and transmitter
  • Maximum Jitter of 1/clk
  • Inactive during Idle periods with Break signal
  • Small footprint of about 12 macro-cells per encoder and Decoder
  • Full Duplex or Half-Duplex with Bus Grant/Hold Signalization
  • Low Power Consumption


  • Low Cost High-Speed Chip to Chip Communication: i.e. clock of 150 MHz yields effective rate of 43 Mbps
  • Low Cost (SERDES-less) FPGA 150 Mbps Inter-connection
  • Interface to Quartz-less Sensors: RC oscillator based sensor exposed to wide temperature stresses
  • Automotive replacement for low-cost LIN bus: removes clock alignment period
  • Alternative Technology to 1-Wire
  • Manchester Modulation Replacement: improves bandwidth efficiency and reduces clock speed or recovery logic complexity
  • A/D Opto-isolation: reduces number of SPI signals, cost of digital isolators, and PCB size
  • MCU single-pin tracing, communication, debugging


  • Sensors
  • Robotics
  • Industry

Comparison Table

Modulation Max Speed Signal Bandwidth Clock/Data Recovery Clock Tolerance Idle to 1st Bit Complexity / Cost
URSI Gbps 0.875 x rate 3.5x Oversample ±20% <3 bits Low
USB Full-speed Mbps 0.6 x rate 4x Oversample ±0.2% + Preamble <10 bits Medium
Manchester Gbps 1.0 x rate 5x Oversample, PLL Preamble Sync 2..64 bits Low / Medium
NRZI UART Mbps 0.6 x rate 8..16x Oversample ±2% <3 bits Low
NRZI + 8b10, … Gbps 0.6 x rate PLL CDR Preamble Sync <80 bits Higher