Isotel - Mixed Signal Simulation

Introduction to Open Source Spice Mixed Signal & Verilog SimulationΒΆ

In this article you will learn how to perform a mixed signal simulation in ngspice and verilog using yosys verilog synthesis tool of a sine generation with pseudo-random-sequence generator demo project.

Uros Platise, 19. March 2017

Designing embedded applications typically involves analog and digital worlds, from simple micro-controllers, more comprehensive micro-controllers featuring programmable digital and analog logic, or it could refer to a new chip designs. To be able to verify the concepts we strive for simulation tools that could verify both worlds together, not only as a mixed-signal simulation but also to be able to include Verilog and other languages too. Such solutions are provided by commercial packages each having some benefits and drawbacks. Here we represent an open-source free to use solution thanks to open-source projects which runs on Linux and MAC and also Windows.