Isotel - Mixed Signal Simulation

Bringing Open-Source Tools Together

Key challenge was to find a working combinations of mature packages to get a usable and working solution of Verilog simulation with mixed-signal spice. Here is the list of open-source software that you will need to begin with mixed-signal and Verilog simulations:

ngSpice - Mixed Signal Simulation

http://ngspice.sourceforge.net/images/nglogo.jpg

Spice originally developed in Berkeley has gone many ways and it’s concepts and core can be found in numerous forks. Here we propose a very well packaged version of spice called ngspice featuring:

  • standard spice core based on spice 3f4
  • mixed signal xspice core
  • extension to verilog-A models
  • T-CAD spice simulation
  • tcl scripting
  • and more.

It’s a part of every linux distribution. Installation procedure is described in user manual.


Yosys - Verilogy RTL synthesis

http://www.clifford.at/yosys/images/show_rtl.png

Yosys developed by Clifford Wolf is a framework for Verilog RTL synthesis with extensive Verilog-2005 support provides a basic set of synthesis algorithms for various application domains. Selected features and typical applications:

  • Process almost any synthesizable Verilog-2005 design
  • Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
  • Built-in formal methods for checking properties and equivalence
  • Mapping to ASIC standard cell libraries (in Liberty File Format)
  • Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
  • Foundation and/or front-end for custom flows

Installation procedure is described in user manuals.


iverilog - Icarus Verilog

http://iverilog.icarus.com/_/rsrc/1302225644705/config/customLogo.gif?revision=5

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format.

Written by Stephen Williams is one of the most popular free verilog simulators. It’s a part of every linux distribution, for details on installation see Installation Guide.


gtkwave - viewer

http://gtkwave.sourceforge.net/splash_512.gif

GTKWave is an analysis tool used to perform debugging on Verilog or VHDL simulation models. GTKWave has been developed to perform debug tasks on large systems on a chip and has been used in this capacity as an offline replacement for third-party debug tools. It features two interlocking tools:

  • gtkwave, is the waveform analyzer and is the primary tool used for visualization, and
  • rtlbrowse, is used to view and navigate through RTL source code.

It’s a part of every linux distribution. Installation instructions and user guide can be found on this link.


graphviz - Visualization tool

http://www.graphviz.org/gvicons/doc-graphviz.png

Graph visualization is a way of representing structural information as diagrams of abstract graphs and networks. It is needed to display synthesized verilog output from the Yosys.

It’s a part of every linux distribution, for other systems please follow the download page.